1. Field of the Invention
A phase locked loop circuit is commonly arranged for comparing the oscillator frequency and phase of a voltage controlled oscillator with a reference signal in a phase comparator and with the use of a resultant output from the phase comparator, controlling an oscillator output from the voltage controlled oscillator to coincide in phase and frequency with the reference signal. The present invention relates to an improved phase locked loop circuit for enabling step multiplication of frequency in a semiconductor integrated circuit such as a microprocessor.
2. Description of the Related Art
A phase locked loop (referred to as a PLL hereinafter) according to the present invention is commonly incorporated in a semiconductor integrated circuit for subject to a pulse waveform and its principles will be no further explained in this description. The principles of PLL is described in more detail in "Phase lock Techniques" F. M. Gardner Second ed., by John Wiley & Sons N.Y. in 1979.
A prior art which is most closely associated with the present invention will then be described referring to FIGS. 11 to 15. FIG. 11 is a block diagram showing a basic PLL circuit in which the oscillator output is a pulse waveform having a frequency which equals two times that of the reference signal. There are provided a phase comparator 1 of a type best shown in FIG. 12, a charge pump 2, a lowpass filter 3, both being arranged in common as shown in FIG. 13, a voltage controlled oscillator 4 of ring oscillator type shown in FIG. 14, and a divider 5 commonly containing a D-type flip-flop as shown in FIG. 15. Also, a similar PLL is disclosed in "Design of PLL-based Clock Generation Circuits" by D. Jeong et al., an article in IEEE J. Solid-state circuits, vol. SC-22, NO. 2, April 1987, pp. 255 to 261.
The operation of the prior art PLL shown in FIG. 11 will now be described. The phase comparator 1 compares an output 8 of the divider 5 with a reference signal 6 and produces a pulse output corresponding to a phase difference between the two pulse waves. The charge pump 2 converts the pulse output into a current pulse which is in turn smoothed by the lowpass filter 3 to a DC voltage. The voltage controlled oscillator 4 generates oscillation at a given frequency corresponding to the current voltage. An oscillator output 7 is divided by the divider 5 into 1/2 frequency divider outputs which are then fed to the phase comparator 1.
In common, just after initial energization, the voltage controlled oscillator 4 remains not synchronized with the reference signal and produces oscillation at an arbitrary frequency not associated with the reference signal 6 (or if any, provides no oscillation). When the divider output 8 is lower in frequency than the reference signal, the phase comparator 1 delivers a low level pulse from an UP terminal thereof. As a result, the control voltage transmitted from the charge pump 2 and the lowpass filter 3 to the voltage controlled oscillator 4 is increased and thus, the frequency of oscillation will increase. On the other hand, when the divider output 8 is higher in frequency than the reference signal 6, the phase comparator 1 delivers a low level pulse from a DOWN terminal thereof. The low level pulse is then smoothed by the charge pump 2 and the lowpass filter 3 so that the control voltage to the voltage controlled oscillator 4 is attenuated. Thereby, the oscillation frequency will be declined.
As understood, when the frequency of the divider output 8 tends to deviate from the predetermined frequency of the reference signal 6, a negative feedback is induced. Accordingly, the divider output 8 remains oscillating at a frequency adjacent to that of the reference signal. The synchronization can be achieved by an appropriate loop gain in the entire PLL circuit and a time constant of the lowpass filter 3. Finally, a pulse wave having a frequency of 2 times that of the reference signal 6 will be delivered from the output 7 of the voltage controlled oscillator.
The components of the PLL shown in FIG. 11 will be described in more detail.
[Phase comparator]
The phase comparator illustrated in FIG. 12 is arranged to accept a reference signal f.sub.REF and a signal output f.sub.VCO of the voltage controlled oscillator (or the divider) and produce an output determined by comparing between the trailing edges of the two signals. If the decay of f.sub.REF comes earlier, a pulse is delivered from the UP terminal. If the decay of f.sub.VCO comes earlier, a pulse is supplied from the DOWN.
FIG. 16 illustrates a timing chart in which the oscillation frequency f.sub.VCO (i.e. a frequency after the division) is lower than the reference signal f.sub.REF. The UP terminal becomes a low level in response to the decay of f.sub.REF and remains at the low level until the decay of f.sub.VCO is detected. As f.sub.VCO is lower in frequency than f.sub.REF, the UP is almost constantly held at the low level. On the contrary, the DOWN remains at a high level.
The phase comparator shown in FIG. 12 is arranged in symmetry for f.sub.REF and f.sub.VCO. When f.sub.VCO is higher in frequency than f.sub.REF, the UP and the DOWN come reversed from their states shown in FIG. 16; the UP remains at a high level and the DOWN remains at a low level. Hence, the states of both the UP and DOWN are determined by the high/low relation in frequency between two pulses having different frequencies regardless of phase difference so that the phase comparator acts as a frequency comparator. FIG. 17 shows a timing chart in which f.sub.REF and f.sub.VCO are nearly identical in frequency to each other and different in phase. A low level pulse having a time length corresponding to a time difference (phase difference) between the decays of f.sub.REF and f.sub.VCO passes either the UP or DOWN terminal. The operation of the phase comparator shown in FIG. 12 will now be described with respect to gate means.
The phase comparator contains four RS flip-flops 22, 23, 24 and 25 consisting of pairs of 2-input NAND gates 12 and 13, 12a and 13a, 14 and 15, and 14a and 15a respectively. A 4-input NAND 16 is thus assigned as a reset for the four RS flip-flops. The phase comparator is reset to an initial state when the 4-input NAND 16 delivers a low level pulse. At the time, the UP and DOWN terminals are also at high level. If both f.sub.REF and f.sub.VCO are held at high level, the outputs of the 2-input NANDs 12 and 12a are at low level and the outputs of the 2-input NANDs 14 and 14a are at high level.
At the initial state, the output of the 4-input NAND 16 is returned to a high level. Then, if f.sub.REF drops, for example, to a low level, the output of 2-input NAND 12 turns to high and the output of the 2-input NAND 13 (i.e. the UP terminal) turns to low. By now, three of four inputs to the 4-input NAND 16 are at a high level while the one from the 2-input NAND 12a is kept low. While f.sub.VCO remains high, a change in f.sub.VCO doesn't affect the phase comparator. In short, at the time, this circuit is waiting for variation of f.sub.VCO.
When f.sub.VCO drops to a low level, the output of the 2-input NAND 12a turns to high. Hence, all the outputs of the 2-input NANDs 12, 12a, 14 and 14a are held at a high level and thus, the 4-input NAND 16 delivers a low level signal causing the RS flip-flops 22, 23, 24 and 25 to be reset. As the result, the UP is turned to a high level and the entire circuit will be returned to the initial state.
When f.sub.VCO is shifted to a low level from the initial state, the action will be just a reverse of the foregoing and no further described.
When both f.sub.REF and f.sub.VCO are simultaneously shifted from a high level in the initial state to a low level, the 4-input NAND 16 delivers a low level signal causing the circuit to be reset. Hence, the UP and DOWN terminals temporarily drop to the low level and then, return to the original high level. This momentary level shift results in a spike which can be eliminated by wave modulating the outputs of the UP and DOWN terminals. Accordingly, the coincidence of f.sub.REF and f.sub.VCO in phase and frequency allows the UP and DOWN outputs of the phase comparator to remain practically at a high level constantly.
[Charge pump+lowpass filter]
The charge pump 2 and the lowpass filter 3 will be described referring to FIG. 13. The charge pump 2 is arranged to actuate upon receiving two, UP and DOWN, pulse signals from the phase comparator 1. When UP is low, a P-channel transistor 30 of the charge pump 2 is switched on to feed a current to the lowpass filter 3. When DOWN is low, an N-channel transistor 31 is turned on to transfer a current from the lowpass filter 3 towards the GND potential. When both UP and DOWN are at high level, the output of the charge pump 2 is kept in a high impedance state, hence no change of state for the lowpass filter 3. The current output from the charge pump 2 is smoothed in the low pass filter 3 to a control voltage which is supplied to the voltage controlled oscillator 4.
More specifically, the circuit arrangement shown in FIG. 13 will operate in the following manner. When the reference signal and the oscillator output (or a divider output) are quite different in frequency from each other, either UP or DOWN is almost constantly maintained to a low level, the charge pump feeds a current and the output of the lowpass filter 3 increases or decreases with a specific time constant (R1+R2) C. When the two frequencies of the reference signal and the oscillator output (or the divider output) become nearly equal to each other, a series of short pulses are applied at equal intervals of a time (a period in the reference signal) to the input of the charge pump 2 which in response produces a current pulse. Then, a pulse output voltage of the lowpass filter 3 is iR.sub.2 where i is the magnitude of a current pulse.
This pulse is fed to the voltage controlled oscillator where the frequency is shifted by a given time equal to a time length of the pulse so that the phase difference is corrected. If R.sub.2 is too small, the phase compensation will be less effective and hardly ensure stable oscillation. Also, if R.sub.2 is too great, the pulse determined by iR.sub.2 becomes excessively high and the phase compensation will be over the proper level, thus resulting in unstable oscillation. For the proper setting of R.sub.1, R.sub.2 and C refer to the book, "Phase lock Technique" described previously.
[Voltage controlled oscillator]
The voltage controlled oscillator will now be described referring to FIG. 14, which consists of a buffer amplifier 38 and a ring oscillator 39. The buffer amplifier 38 is arranged to produce upon receiving an output from the lowpass filter 3 a control voltage for supply to the ring oscillator 39. The output of the lowpass filter 3 is low in load driving capability and also, a couple of control lines 40 and 41 in between tend to accumulate noises resulting from switching movements of transistors 35 and 36 (more particularly, caused by the coupling capacitance between drain and gate). It is thus needed for providing the buffer amplifier 3 between the lowpass filter 3 and the ring oscillator 39.
The ring oscillator 39 is provided in which an odd number of functional rows (stages), each row consisting of an inverter composed of a P-channel transistor 35 and an N-channel transistor 36, a P-channel transistor 34 coupled to the P-channel transistor 35, and an N-channel transistor 37 coupled to the N-channel transistor 36, are aligned in the cascade arrangement. The output of the last row is coupled to the input of the first row. Both the P- and N-channel transistors 34 and 37 are varied in "on" resistance by the control voltage so that the switching delay in the inverter of the transistors 35 and 36 can change.
The oscillation in the ring oscillator is induced by transmission of a switching delay of the inverter and its cycle is determined by a duration in which the switching delay circulates 2 times in the ring oscillator. If the switching delay of the inverter is defined .tau..sub.a and the number of the inverter rows is n, the oscillating cycle is expressed as: EQU T=2n.tau..sub.a
Then, the oscillator frequency f is obtained from: ##EQU1## In general, the number n of the inverter rows is fixed and the oscillator frequency can be controlled by .tau..sub.a. Hence, the ring oscillator 39 generates a higher rate of the oscillator frequency when the input voltage to the buffer amplifier 38 is increased and a lower rate when it is decreased.
[Divider]
The divider 5 will now be described referring to FIG. 15. The divider illustrated in FIG. 15 is substantially a D-type flip-flop in which a signal supplied to the port D is polarity inverted in response to the rise of a clock CK and transferred to the port Q. Accordingly, through the feedback of Q output to D input, the Q output is polarity inverted corresponding to each rise in the clock CK. Although this action is associated with the division by 2, more cascade connections of the D flip-flop can be formed to realize division by n.
The phase locked loop circuit employing this ring oscillator, which is not associated with the present invention, will encounter a difficulty in the action if the range of the frequency of a reference signal input is wide.
When a high frequency reference signal is input, the ring oscillator should produce a high frequency output signal and thus, the period required for the cycle movement of a switching wave across the inverters needs to be shortened. For the purpose, a less number of the inverter rows will be desired. If the inverter rows are provided in large number instead, in spite of rising of the control voltage, the period of cycling across the inverters becomes extended and inappropriate to the high frequency.
Also, when a low frequency of the reference signal is input, the period required for circulation of a timing signal within the ring oscillator becomes longer in order to produce a low frequency output corresponding to the low frequency reference signal input. In general, it is thus needed to increase the rows in the ring oscillator in quantity of inverters rows for low frequency.
However, in the foregoing arrangement having a reduced number of the rows for high frequency output, the only possible provision for lengthening the cycle of the oscillation is to increase a delay time in each inverter row of the ring oscillator. This causes a potential shift in the inverter at output slow and the inverter itself will thus show a tendency to draw an unnegligible amount of external noise and will be less stable in oscillation.
In addition, a ring-oscillator having little number of inverter rows tends to vary its oscillation frequency greater by a little change of control voltage than a ring-oscillator having large number of inverter rows.
Therefore, the former is more sensitive than the latter to the noise superposed on the control line.
It is now understood that more number of the rows in the ring oscillator are preferably employed for accepting low frequency input signals.
A problem still lies that the PLL having a ring oscillator of a given number of rows is unlikely to provide a good performance for the wide range of frequencies.